1. Field of the Invention
The present invention relates generally to memory modules, and more particularly, to parallel testing within a memory module for increased efficiency.
2. Description of the Related Art
FIG. 1 shows a conventional parallel testing apparatus 100 for a semiconductor memory device. Referring to FIG. 1, the conventional parallel testing apparatus 100 includes an amplification unit 20, global input/output lines (GIO), a comparison unit 30, and an output buffer unit 40. The amplification unit 20 amplifies data received from memory cells of a memory bank 10.
The amplified data is coupled to the comparison unit 30 via the global input/output lines. The comparison unit 30 compares such amplified data with exclusive OR gates (not shown) and outputs a result of the comparison. Each exclusive OR gate receives four bits of the amplified data selected by one of column lines CD0 through CD3 and compares the received four bits of the amplified data. If the four bits to an exclusive OR gate are the same, the exclusive OR gate outputs a data value of “0”. Otherwise, the exclusive OR gate outputs a data value of “1”.
The data values output from the exclusive OR gates are sent to external testing apparatus through the output buffer 40. The external testing apparatus then determines whether the memory device is defective from received data values.
The conventional parallel testing apparatus 100 is directed to parallel testing one memory bank 10 of one memory device (i.e., memory chip). As storage capacity of the memory increases, the number of memory banks increases. So, the amount of data subject to simultaneous testing is limited when using the conventional parallel testing method, and more testing time is needed as memory density increases.
In addition, it is desirable that the test system may analyze data bits from a memory device. However, the conventional parallel testing apparatus 100 does not output any stored data bits from the memory device 10. Furthermore, a memory module is comprised of a plurality of memory devices (i.e., a plurality of memory chips). Thus, an efficient mechanism for efficient testing of the plurality of memory chips of the memory module is desired.